{"id":238300,"date":"2016-02-01T00:00:00","date_gmt":"2016-02-01T08:00:00","guid":{"rendered":"https:\/\/new-cm-edgedigital.pages.dev\/en-us\/research\/msr-research-item\/energy-efficient-address-translation\/"},"modified":"2018-10-16T20:05:44","modified_gmt":"2018-10-17T03:05:44","slug":"energy-efficient-address-translation","status":"publish","type":"msr-research-item","link":"https:\/\/new-cm-edgedigital.pages.dev\/en-us\/research\/publication\/energy-efficient-address-translation\/","title":{"rendered":"Energy-Efficient Address Translation"},"content":{"rendered":"
\n

Address translation is fundamental to processor performance. Prior work focused on reducing Translation Lookaside Buffer (TLB) misses to improve performance and energy, whereas we show that even TLB hits consume a significant amount of dynamic energy.<\/p>\n

To reduce the energy cost of address translation, we first propose Lite<\/em>, a mechanism that monitors the performance and utility of L1 TLBs, and adaptively changes their sizes with way-disabling. The resulting TLBLite<\/em> organization opportunistically reduces the dynamic energy spent in address translation by 23% on average with minimal impact on TLB miss cycles. To further reduce the energy and performance overheads of L1 TLBs, we also propose RMMLite<\/em> that targets the recently proposed Redundant Memory Mappings (RMM) address-translation mechanism. RMM maps most of a process\u2019s address space with arbitrarily large ranges of contiguous pages in both virtual and physical address space using a modest number of entries in a range TLB. RMM Lite<\/em> adds to RMM an L1-range TLB and the Lite mechanism. The high hit ratio of the L1-range TLB allows Lite to downsize the L1-page TLBs more aggressively. RMMLite<\/em> reduces the dynamic energy spent in address translation by 71% on average. Above the near-zero L2 TLB misses from RMM, RMMLite<\/em> further reduces the overhead from L1 TLB misses by 99%.<\/p>\n

These proposed designs target current and future energyefficient memory system design to meet the ever increasing memory demands of applications.<\/p>\n<\/div>\n

<\/p>\n","protected":false},"excerpt":{"rendered":"

Address translation is fundamental to processor performance. Prior work focused on reducing Translation Lookaside Buffer (TLB) misses to improve performance and energy, whereas we show that even TLB hits consume a significant amount of dynamic energy. To reduce the energy cost of address translation, we first propose Lite, a mechanism that monitors the performance and […]<\/p>\n","protected":false},"featured_media":0,"template":"","meta":{"msr-url-field":"","msr-podcast-episode":"","msrModifiedDate":"","msrModifiedDateEnabled":false,"ep_exclude_from_search":false,"_classifai_error":"","msr-author-ordering":null,"msr_publishername":"IEEE - Institute of Electrical and Electronics Engineers","msr_publisher_other":"","msr_booktitle":"","msr_chapter":"","msr_edition":"IEEE International Symposium on High Performance Computer Architecture (HPCA)","msr_editors":"","msr_how_published":"","msr_isbn":"","msr_issue":"","msr_journal":"","msr_number":"","msr_organization":"","msr_pages_string":"631-643","msr_page_range_start":"631","msr_page_range_end":"643","msr_series":"","msr_volume":"","msr_copyright":"","msr_conference_name":"IEEE International Symposium on High Performance Computer Architecture (HPCA)","msr_doi":"10.1109\/HPCA.2016.7446100","msr_arxiv_id":"","msr_s2_paper_id":"","msr_mag_id":"","msr_pubmed_id":"","msr_other_authors":"Vasileios Karakostas, Jayneel Gandhi, Adri\u00e1n Cristal, Mark D. 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